1. Field of the Invention
The present invention generally relates to a nonvolatile memory device and a method for fabricating its gate structure, and more specifically to a nonvolatile memory device having an Electrically Erasable-Programmable Read-Only Memory (EEPROM) and a stacked gate latch transistor, and a method for fabricating the EEPROM and latch transistor gate structure.
2. Description of the Related Art
U.S. Pat. No. 4,571,704, "Nonvolatile Latch" to F. Bohac and assigned to Hughes Aircraft Company, the assignee of the present invention, discloses a bistable latch circuit which can be electrically programmed to be stable in only one of its two states so that this same state is always set when power is applied to the circuit. The purpose of the nonvolatile latch is to store data, and to retain that data if power is interrupted.
Since the circuitry of the Bohac patent is also applicable in general to the present invention, it will be described in some detail. FIG. 1 is a schematic diagram of the nonvolatile latch 10 disclosed in the Bohac patent comprising four interconnected MOS transistors 12, 14, 16 and 18, and two EEPROMs 20 and 22. Transistors 12 and 14 are CMOS P-channel field effect transistors (FETs) whose sources 24, 26 are coupled together at a node 28. The gate 30 of transistor 12 is coupled to the drain 32 of transistor 14 at a node 34. Similarly, the gate 36 of transistor 14 is coupled to the drain 38 of transistor 12 at a node 40.
Transistors 16, 18 are N-channel latch MOSFETs whose drains 42, 44 are connected to the drains 38, 32 of the P-channel transistors 12, 14 and whose sources 46, 48 are connected to a low supply voltage V.sub.S, typically ground. EEPROMs 20, 22 comprise p-well tie downs 50, 52, floating gates 54, 56 and control gates 58, 60. The floating gates 54, 56 are electrically connected to the gates 62, 64 of latch transistors 16, 18. The EEPROM control gates 58, 60 are connected to the opposing EEPROM p-well tie downs 52, 50 at nodes 66, 68, respectively.
Binary DATA and PROGRAMMING voltages 70, 72 are applied to a programming circuit 74. The PROGRAMMING voltage is also applied to node 28. The programming circuit outputs voltage signals to nodes 66, 68 in accordance with the DATA and PROGRAMMING voltages. When the PROGRAMMING voltage is low, the DATA voltage establishes the binary data value to be stored by the latch. When the PROGRAMMING voltage is high, the stored data is read out of the latch at node 34. The inverse of the stored data can be read out at node 40.
A typical nonvolatile memory could have several thousand nonvolatile latch cells, such as the cell shown in FIG. 1, for storing data. The memory would also include support circuitry for addressing the individual cells, programming the cells and reading out the data. The fabrication process currently used by Hughes Aircraft Company for the nonvolatile latch 10, and specifically for the gate structure, is described in conjunction with FIGS. 2a-2d (which are not to scale) for the EEPROM 20, its latch transistor 16 and P-chann el transistor 12. The fabrication of the P-channel transistor and the problems in controlling its linewidth are common to other P and N-channel transistors on the substrate.
As shown in FIG. 2a, a semiconductor substrate 80 has P-wells 82, 83 that are separated by field oxide regions 84 to form active areas for the EEPROM 20 and the latch transistor 16, respectively. The P-channel transistor is formed directly in the N-substrate. An oxide layer 86 is formed over the substrate and an electron tunnel 88 is etched in the oxide layer above the EEPROM active area 82. A polysilicon layer (not shown) having a thickness of approximately 5000.ANG. is deposited over the substrate, patterned with a photoresist and etched to form the EEPROM floating gate 54 and the latch transistor gate 62 over their respective active areas 82 and 83. A dielectric oxide layer 90 is then formed on the top and sides of the EEPROM floating gate 54 and latch transistor gate 62.
To form the EEPROM control gate 58 and the P-channel transistor gate 30, a second polysilicon layer 92 is deposited over the substrate as shown in FIG. 2b. The layer 92 Generally has a thickness of approximately 5,000.ANG.. However, the deposition process produces a smooth polysilicon layer whose height from the substrate surface decreases smoothly from approximately 10,000.ANG. above the EEPROM floating gate 54 and the latch transistor Gate 62 (the combined thicknesses of the two polysilicon layers) to approximately 5,000.ANG. along the substrate surface. Therefore, the thickness of the deposited polysilicon near either side of the latch transistor gate 62 and EEPROM floating Gate 54 is greater than 5,000.ANG.. A photoresist pattern 94 is patterned over the second polysilicon layer to delineate the EEPROM control gate 58 and the P-chann el transistor gate 30. The exposed polysilicon is etched to a depth of approximately 5000.ANG. to form the EEPROM control gate 58 and the P-channel gate 30 as shown in FIG. 2c.
If the etching process were stopped at this point, polysilicon spacers 96 would be left on either side of the latch transistor gate 62 due to the increased thickness of the second polysilicon layer in these regions. The spacers are approximately 3,000.ANG. wide. The EEPROM control gate 58 covers the floating gate 54, and hence no spacers are formed around the EEPROM.
When the drain and source regions of the latch transistor are subsequently ion implanted, the spacers would block the ions from penetrating the underlying substrate, leaving gaps between a channel area under the latch transistor gate 62 and drain and source regions on either side of the channel. The gaps would seriously increase the channel resistance, thus slowing the latch transistor.
Therefore, as shown in FIG. 2d, the second polysilicon layer is typically overetched, i.e., the etching time is extended beyond the normal time for a given layer thickness, to remove the polysilicon spacers 96, after which the remaining photoresist is dissolved. The normal etching process undercuts the P-channel transistor gate 30 and reduces its width by approximately 0.1.mu. for each 1.mu. of vertical etch. Overetching substantially increases the amount of undercutting. For example, a 3.mu. wide P-channel gate 30 may be undercut so that its actual linewidth is approximately 2.2.mu..
The extent of the undercut is not known prior to etching and will vary from device-to-device, making it very difficult to compensate for the undercut in the original design or to know precisely what the actual gate width is after etching. The poor linewidth control reduces the effective length of the channel, thus changing the performance of the P-channel transistor. If the channel length becomes too short, source-to-drain punchthrough can result, destroying the transistor. Consequently, the P-channel transistor is limited to gate widths greater than 1.mu..
A common practice to diminish the undercutting problem is to reduce the thickness of the dielectric oxide layer 90 and the first polysilicon layer. This reduces the overetching time, which in turn reduces the amount of undercutting. However, a thin dielectric layer reduces the breakdown voltage between the EEPROM floating gate and its control gate. A thin first polysilicon layer will allow ion implantation penetration in the latch transistor's channel during the source/drain implantations which can increase the leakage current in the device.